Job Description

Location: Tolochenaz, Switzerland



Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world -come join our team and see how YOU can make a difference.

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Job Summary:

The candidate must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both technical and leadership skills, while working closely with multi-disciplinary groups to drive & design key aspects of ASIC/pwr mgmt. IC's that meets the requirements of products. Candidate will be lead designer, support verification, and be technical focus on one or more device and/or sections. Candidate will also support pre/post-silicon design validation and support Design/ATE/Application & Systems group.


MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.

Essential Functions:

Support & develop the chip/digital level architecture and functional blocks Provide technical documentation with specifications, block diagrams, and requirements to stakeholders. Collaborate & work with departments/stakeholders including for architectures, requirements, and tradeoffs, including Digital/Analog Design, Application/Test Engineering, & Reliability/Operations to resolve design, application, or test issues. Develop system and chip level simulation verification techniques and methodology. Digital Design (RTL design): ASIC or FPGA from concept to implementation Digital Verification: Development test plans, test benches and automated test cases Knowledge and/or responsibility in synthesis, timing closure, and formal verification. Create scripting to support design and verification automation Estimate and manage time/tasks completion to target schedule

Qualifications:

PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework. 4+ years experience in design plus verification of ASIC or FPGA Broad & Strong knowledge of ASIC development process and digital design techniques. Proficient in standard DV languages (Verilog, SystemVerilog, UVM) and automated regression testcase development, and reporting/tracking coverage metrics. Experience with programming, scripting and automation languages(C/C++, shell, Perl, TCL, Python, etc). Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc. Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc. Good written/verbal communication skills and strong team work/collaboration. Experience with the following is highly desired: Knowledge of power management architectures/applications


I2C, I3C, SPI, USB, PMBUS, I2S, CANOpen, EtherCAT


GITLab or equiv version control


Embedded MCU(ARM) designs and/or firmware development


Previous experience in signal processing and sensors

Location:

SWZ


Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.