Senior Digital Ic Verification Engineer

La Tène, NE, CH, Switzerland

Job Description

The Role


We are looking to expand our team with a

Senior Digital IC Verification Engineer

. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc.



onsemi

(Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world's most complex challenges and leads the way in creating a safer, cleaner, and smarter world.





More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

What You'll Need


Minimum BS/MS in Electrical Engineering or related technical field Minimum 3 years of digital verification experience Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage In-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection Excellent English written and verbal communication skills Eligibility to work in Switzerland
What Else You May Bring


Experience with: Project/task leadership Verification of signal processing components 3rd party verification IP deployment Programming skills - Python, Tcl, embedded software Knowledge of French

What You'll Do


Define the verification strategy and the detailed verification plans for blocks and systems Coordinate/lead the verification activities in the project teams Develop SystemVerilog/UVM environments for blocks and top-level SoCs Debug functional errors in RTL * Participate to verification methodology improvement activities

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Job Detail

  • Job Id
    JD1921536
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    La Tène, NE, CH, Switzerland
  • Education
    Not mentioned